1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly to a method of adjusting a substrate size of liquid crystal display device.
2. Description of the Related Art
A liquid crystal display (LCD) controls a light transmittance of individual liquid crystal cells according to a video signal, thereby displaying image data (images). An active matrix type LCD is suitable for displaying moving images by a switching device that drives the individual liquid crystal cells. Presently, a thin film transistor is commonly used as the switching device in the active matrix type LCD.
FIG. 1 is a perspective view of a liquid crystal display device according to the related art. In FIG. 1, an active matrix type LCD includes a color filter substrate 35 and a thin film transistor (TFT) substrate 36 that are sealed together having a liquid crystal molecules 15 disposed therebetween. In a transmittance type LCD, a backlight unit (not shown) is disposed at a rear portion of the TFT substrate 36, thereby irradiating incident light to the TFT substrate 36. The liquid crystal molecules 15 are injected between the color filter substrate 35 and the TFT substrate 36. Liquid crystal molecules 15 rotate in response to an applied electric field, thereby controlling a transmissivity of the incident light via the TFT substrate 36.
The color filter substrate 35 includes an upper substrate 12 having a color filter 13, a common electrode 14, and a polarizer 11. The color filter 13 and the common electrode 14 are disposed on a rear side of the upper substrate 12. The color filter 13 has color filter layers of red, green and blue disposed in a shape of stripes to transmit specific wavelength bands of the incident light, thereby displaying colored light. A black matrix (not shown) is formed between the color filters 13, thereby absorbing any of the incident light from between adjacent cells.
The TFT substrate 36 includes a lower substrate 16 having a gate line 18, a data line 19, and a polarizer 17. The gate line 18 and the data line 19 are formed to cross each other on a front side of the lower substrate 16. A TFT 20 is formed at the intersection of the gate line 18 and the data line 19, and a pixel electrode 21 is formed in a matrix array in a cell area between the gate line 18 and the data line 19. The TFT 20 switches a data transmission path between the data line 19 and the pixel electrode 21 in response to a scanning signal from the gate line 18 to drive the pixel electrode 21.
The polarizer 11 is disposed on a front side of the upper substrate 12, and the polarizer 17 is attached on a rear side of the lower substrate 16. The polarizers 11 and 17 transmit polarized light along one direction. When the liquid crystal molecules 15 are aligned at a 90° twisted nematic (TN) mode, polarizing directions of the liquid crystal molecules 15 are perpendicular to each other. Alignment films (not shown) are formed on the rear side of the upper substrate 12 and the rear side of the lower substrate 16.
A fabricating process for manufacturing an active matrix type liquid crystal display device includes cleaning the upper and lower substrates 12 and 16, patterning the upper and lower substrates 12 and 16, forming alignment films on the upper and lower substrates 12 and 16, scaling the upper and lower substrates 12 and 16, injecting the liquid crystal molecules between the upper and lower substrates 12 and 16, and mounting and testing the active matrix type liquid crystal display device.
Cleaning the upper and lower substrates 12 and 16 includes a process that eliminates any impurities from the upper and lower substrates 12 and 16 with cleansing agents.
Patterning the upper and lower substrates 12 and 16 includes processes for patterning the upper substrate 12 and patterning the lower substrate 16. The process for patterning the upper substrate 12 includes sequentially forming the black matrix (not shown), the color filter 13, and the common electrode 14. The process for patterning the lower substrate 16 includes forming the gate line 18, the data line 19, the TFT 20, and the pixel electrode 21.
FIG. 2 is a plane view of a thin film transistor (TFT) and a pixel electrode of the liquid crystal display device shown in FIG. 1 according to the related art, and FIG. 3 is a cross sectional view taken along I-I′ of FIG. 2 according to the related art.
In FIGS. 2 and 3, the fabricating process of the TFT 20 begins with a process of depositing a gate metal on an entire surface of the lower substrate 16 by a sputtering method or an electroless plating method. The gate metal includes chromium (Cr), molybdenum (Mo) or an aluminum-alloy metal. The aluminum-alloy metal includes a multilayer structure of Aluminum-Neodymium (AlNd) and Aluminum-Molybdenum (AlMo). Accordingly, the aluminum-alloy metal has a low resistance to compensate for signal delay caused by the molybdenum layer. Subsequently, a mask is aligned on the lower substrate 16, and the gate metal layer is patterned by a photolithographic process that includes exposure and development processes, thereby forming the gate line 18 and the gate electrode 23 of the TFT 20.
Next, an insulating material is deposited on an entire surface of the lower substrate 16 over the gate line 18 and the gate electrode 23 to form a gate insulating layer 31. Inorganic insulating materials such as silicon oxide (SiOx) and silicon nitride (SiNx) may be used to form the gate insulating layer 31.
Next, semiconductor and impurities-doped semiconductor materials are continuously deposited on top of the gate insulating layer 31 by the chemical vapor deposition (CVD) process. Subsequently, the semiconductor and impurities-doped semiconductor materials are patterned by a dry etching process after alignment of a mask to form an active layer 32 and an ohmic contact layer 33. Amorphous silicon or undoped polycrystalline silicon may be used as materials with which to form the semiconductor material. Likewise, amorphous silicon or polycrystalline silicon doped with n-type or p-type impurities at a high concentration may be used as materials with which to form the impurities-doped semiconductor material.
A source and drain metal layer is deposited on an entire surface of the lower substrate 16 including the active layer 32 and the ohmic contact layer 33. Molybdenum (Mo), titanium (Ti), and tantalum (Ta) are used as the source and drain metal layer. Subsequently, the source and drain metal layer is patterned by wet etching process after alignment of a mask. The patterned source and drain metal layer form a source electrode 22, a drain electrode 24, and a storage capacitor electrode 27 of the TFT 20. The source electrode 22 is connected to the data line 19 and the storage capacitor electrode 27, and overlaps with the gate line 18 and the gate insulating layer 31. The ohmic contact layer 33 is dry-etched to form portions over the source electrode 22 and the drain electrode 24, whereby a central portion of the ohmic contact layer 33 is eliminated.
A passivation layer 34 including an inorganic or organic insulating film is formed on the lower substrate 16 including the source electrode 22 and the drain electrode 24. Silicon oxide (SiOx) and silicon nitride (SiNx) can be used for the inorganic insulating film, and an acrylic organic compound, benzocyclobutene (BCB) and perfluorocyclobutane (PFCB), can be used for the organic insulating film. Then, contact holes 25 and 26 are formed in the passivation layer 34 exposing one end of the drain electrode 24 and one end of the storage capacitor electrode 27.
A transparent conductive material is deposited on an entire surface of the passivation layer 34 where the contact holes 25 and 26 are formed. Any one of indium tin oxide (ITO), tin oxide (TO) or indium zinc oxide (IZO) can be used for the transparent conductive material. Subsequently, the transparent conductive material is patterned by a mask alignment process and a dry etching process. The patterned transparent conductive material becomes the pixel electrode 21. The pixel electrode 21 is electrically connected to the drain electrode 24 of the TFT 20 via the contact hole 25. In addition, an upper projected portion 21a of the pixel electrode 21 is electrically connected to the storage capacitor electrode 27 via the contact hole 26.
When the passivation layer 34 is made of the organic insulating material with low dielectric constant for high aperture ratio, a side of the pixel electrode 21 overlaps with the gate line 18 or the data line 19, as shown in FIG. 2.
During the substrate sealing process, an alignment film is spread on the upper and lower substrates 12 and 16, and rubbed. Subsequently, the upper and lower substrates 12 and 16 are sealed by use of a sealant. Then, a liquid crystal injecting process and injection hole sealing process are sequentially conducted after the substrates sealing process.
During mounting of the active matrix type liquid crystal display device, a tape carrier package (TCP) that includes integrated circuits (IC) is mounted to function as a gate drive IC and a data drive IC (not shown) connected to pads of the gate and data lines 18 and 19 formed on the lower substrate 16. During testing of the active matrix type liquid crystal display device, a judgment is made whether or not the active matrix type liquid crystal display device functions properly. Specifically, during the testing, bad pixels are detected by applying test pattern data to the data line 19 and applying scanning signals to the gate line 18 to drive the liquid crystal cell. The bad pixels are detectable as dark points.
During the fabricating process for manufacturing the active matrix type liquid crystal display device, the size of the upper and lower substrates 12 and 16 are changed due to stresses applied to the upper and lower substrates 12 and 16 during deposition of materials. Accordingly, if the sizes of the upper and lower substrates 12 and 16 are changed in differing amounts, the TFT substrate 36 and the color filter substrate 35 will not be accurately sealed. The stresses are defined as a force applied to the upper and lower substrates 12 and 16 per unit area, and the unit is expressed by “dyne/cm2.”
FIG. 4A is a cross sectional view of a bare glass substrate where no deposition layer is formed according to the related art, FIG. 4B is a cross sectional view of a substrate during a compressive mode by a deposition layer according to the related art, and FIG. 4C is a cross sectional view of a substrate during a tensile mode by a deposition layer according to the related art. In FIG. 4A, a bare glass substrate 42 exists having parallel planar surfaces where no deposition layer is formed.
In FIGS. 4B and 4C, when a deposition layer 41 is deposited on a substrate 42, stress is imparted to the substrate 42, thereby deforming of the substrate 42. The stress caused by the deposition layer 41 can vary in size and direction according to physical properties of the substrate 42 and the deposition layer 41. The physical properties include internal factors such as differences between thermal expansion coefficients of the substrate material and the deposition layer material, and external factors such as deposition conditions. For example, in FIG. 3, the gate insulating layer 31 and/or the passivation layer 34 have a significant influence upon stresses imparted to the substrate 16.
In FIG. 4B, the deformation of the substrate 42 is due to stress generated by a compressive mode where edges of the substrate 42 bend upward. In the compressive mode, a length of the substrate 42 increases because a force is imparted to the substrate 42 from a central portion toward the edges.
In FIG. 4C, the deformation of the bare glass substrate 42 is due to stress generated by a tensile mode where edges of the bare glass substrate 42 bend downward. In the tensile mode, a length of the substrate 42 decreases because a force is imparted to the substrate 42 from the edges toward a central portion.
FIG. 5 is a cross sectional view showing a difference between a color filter substrate and a TFT substrate due to a compressive mode according to the related art.
FIG. 5 is a cross sectional view showing a difference between a color filter substrate and a TFT substrate due to a compressive mode according to the related art. In FIG. 5, stress is imparted to the TFT substrate 36 in the compressive mode such that the size of the TFT substrate 36 increases. Likewise, stress is imparted to the color filter substrate 35 in the tensile mode such that the size of the color filter substrate 35 decreases. The resulting differences between the increased size of the TFT substrate 36 and the decreased size of the color filter substrate 35 generates significant misalignment.
FIG. 6 is a perspective view showing light leakage resulting from misalignment of a color filter substrate and a TFT substrate according to the related art. FIG. 7 is a cross sectional view showing light leakage resulting from misalignment between a black matrix on the color filter substrate and a metal pattern on the TFT substrate shown in FIG. 6 according to the related art.
In FIGS. 6 and 7, if the TFT substrate 36 and the color filter substrate 35 are not accurately sealed, the metal patterns 72, which include the gate and data lines 18 and 19, are not in proper registration with the black matrix 71 formed on the color filter substrate 35. Accordingly, light leakage occurs between adjacent cells because of the inaccurate registration of the black matrix 71 and the metal patterns 72, thereby deteriorating contrast of the display device.